Search - VHDL simple calculator

[Other resource] calculation2

Description: 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
Platform: | Size: 2729 | Author: 刘西圣 | Hits:

[Other] VHDL1

Description: a simple calculator with vhdl operators performing calculator operation
Platform: | Size: 1104 | Author: mak chi ho | Hits:

[VHDL-FPGA-Verilog] calculation2

Description: 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0-- 100 within a simple calculator function in the source code. including the four arithmetic operations function
Platform: | Size: 2048 | Author: 刘西圣 | Hits:

[Other] VHDL1

Description: a simple calculator with vhdl operators performing calculator operation
Platform: | Size: 1024 | Author: mak chi ho | Hits:

[VHDL-FPGA-Verilog] 61EDA_D1051

Description: 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
Platform: | Size: 24576 | Author: 缺打打 | Hits:

[VHDL-FPGA-Verilog] erwertwerwe

Description: 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
Platform: | Size: 11264 | Author: 缺打打 | Hits:

[VHDL-FPGA-Verilog] 1

Description: 用VHDL编写的计算器：能实现简单的加减乘除四则运算 -Prepared using VHDL Calculator: able to achieve simple addition and subtraction, multiplication and division 4 computing
Platform: | Size: 4096 | Author: 邓法群 | Hits:

[VHDL-FPGA-Verilog] calculator

Description: VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
Platform: | Size: 314368 | Author: hodog | Hits:

[VHDL-FPGA-Verilog] calculator

Description: 用VHDL在quartus2下实现的计算器。输入为4*4矩阵键盘，输出为共用数据线的数码管。可以实现简单数学运算、逻辑运算、进制转换、连续运算等功能。-Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, logical operations, binary conversion, continuous operations and other functions.
Platform: | Size: 1276928 | Author: jizhen | Hits:

[Algorithm] dp1sol

Description: Simple Binary Calculator
Platform: | Size: 131072 | Author: Klon | Hits:

[Other] Calculator_altera

Description: 简易计算器，采用VHDL编写，能进行加减运算-Simple calculator, using VHDL writing, addition and subtraction operations can be carried out
Platform: | Size: 438272 | Author: chen | Hits:

[Other] jianyijisuanqiVHDL

Description: 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
Platform: | Size: 1018880 | Author: 倪萍波 | Hits:

[Other] test

Description: 简易计算器 2位数字的加减乘除用VHDL编程在实验箱上实现-Simple Calculator 2-digit addition and subtraction, multiplication and division using VHDL programming to achieve in the experimental box
Platform: | Size: 3794944 | Author: 方婷 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 计算器实现功能简单容易实现可自我调试至更强大性能，不喜勿下-Calculator features simple and easy to achieve self-commissioning to a more powerful performance, do not like not under
Platform: | Size: 5120 | Author: shangrrw | Hits:

[VHDL-FPGA-Verilog] verilog_calculator

Description: 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
Platform: | Size: 16384 | Author: 刘涛 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: It s a simple calculator of addition and multiplication using a simple stack, with multiple test benches. The files test-button and debounce are for the use on a board for the correct functionality of the input buttons.
Platform: | Size: 17408 | Author: mandara | Hits:

[VHDL-FPGA-Verilog] Simple-calculator

Description: Simple calculator using VHDL coding
Platform: | Size: 1290240 | Author: kien kien | Hits:

[VHDL-FPGA-Verilog] 123

Description: 基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
Platform: | Size: 5670912 | Author: 于智同 | Hits:

[Other] vhdl---calculator

Description: 基于vhdl语言编写的简易计算器程序，其中主要功能有加减乘和清除，确定等，可实习现连续运算。输出使用七段数码管输出，输入采用拨码开关的方式输入。若计算结果超过99999，蜂鸣器自动报警。-Vhdl language based on simple calculator program, where the main function, subtraction, multiplication and clear, determined, can now practice continuous operation. Output using seven-segment LED output, input mode using DIP switch inputs. If the calculation results of more than 99,999, the buzzer alarm.
Platform: | Size: 1817600 | Author: 张圆 | Hits:

[VHDL-FPGA-Verilog] entity-fp-is

Description: 简易计算器4*4矩阵键盘输入,多个数值vhdl代码(Simple calculator 4* 4 matrix keyboard input, multiple values vhdl codes)
Platform: | Size: 12288 | Author: 刘飞 | Hits:

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[Other resource] calculation2

[Other] VHDL1

[VHDL-FPGA-Verilog] calculation2

[Other] VHDL1

[VHDL-FPGA-Verilog] 61EDA_D1051

[VHDL-FPGA-Verilog] erwertwerwe

[VHDL-FPGA-Verilog] 1

[VHDL-FPGA-Verilog] calculator

[VHDL-FPGA-Verilog] calculator

[Algorithm] dp1sol

[Other] Calculator_altera

[Other] jianyijisuanqiVHDL

[Other] test

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] verilog_calculator

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] Simple-calculator

[VHDL-FPGA-Verilog] 123

[Other] vhdl---calculator

[VHDL-FPGA-Verilog] entity-fp-is

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